1. Field of the Invention
The present invention relates to a sense amplifier of a type static RAM, and more particularly to a high speed sense amplifier of the current detection type formed using bipolar transistors.
2. Description of the Related Art
Memory circuits including a sense amplifier of the current detection type in which Bip elements are used are conventionally known, and an exemplary one of the conventional memory circuits is shown in FIG. 5. Referring to FIG. 5, in the memory circuit shown, NPN transistors Q1, Q2 and Q3 serve as elements for selecting a bit line pair B1 and B2. When a bit line selection terminal VYIN1 exhibits a high potential, the bit line pair B1 and B2 is selected by the NPN transistors Q1, Q2 and Q3 and current flows through constant current sources IR1, IR2 and IY. NPN transistors Q4 and Q5 and constant current sources IB1 and IB2 are provided to raise the potentials of the bit lines when the bit line pair is not selected. The emitter terminals of NPN transistors Q6 and Q7 are connected to the bit lines B1 and B2 while the collector terminals of the NPN transistors Q6 and Q7 are connected to the emitter terminals of NPN transistors Q8 and Q9 by data lines D1 and D2, and resistors Rs1 and Rs2 for converting currents, which flow when memory cells 1 connected to the bit line pair B1 and B2, are not selected, into voltages. Control terminals VR1 and VR2 connected to the base terminals of the NPN transistors Q6 and Q7 both exhibit a high potential upon reading of data, but one of control terminals VR1 and VR2 exhibits a low potential upon writing of data. The base terminals of the NPN transistors Q8 and Q9 are connected to a constant voltage source VBB so that the data lines D1 and D2 always exhibit a fixed voltage.
In operation, when the memory cells 1 connected to the bit lines B1 and B2 are not to be accessed, the bit line selection terminal VYIN1 exhibits a low potential, and the terminals VR1, VR2 and VYY exhibit high potentials.
In this instance, if the potential at the terminal VYY is set to a value higher than the voltages at the terminals VR1 and VR2, then current flows through the constant current sources IB1 and IB2 via the transistors Q4 and Q5. Consequently, the potentials of the bit lines B1 and B2 exhibit values lower by a voltage Vf1, which appears between the emitter and the base of each transistor, than the voltage at the terminal VYY. Then, where the voltages at the control terminals VR1 and VR2 are set to voltages with which the bipolar transistors do not operate with respect to the potentials of the bit lines, no current flows through the NPN transistors Q6 and Q7.
Accordingly, even if the voltage of a word line VX2 rises until MOS transistors MT1 and MT2 of one of the memory cells 1 are put into a conducting state, current is supplied only from the NPN transistors Q6 and Q7 and no influence is had on current which flows through the data lines D1 and D2.
In a reading operation, the potential of the selection terminal VYIN1 for the bit line pairs B1 and B2 rises first. Consequently, the NPN transistors Q1 and Q3 are put into a conducting state and the bit lines B1 and B2 and the constant current sources IR1 and IR2 are connected to each other so that current begins to flow therebetween, respectively. Thereupon, since also the NPN transistor Q2 is put into a conducting state, the potentials at the bases of the NPN transistors Q4 and Q5 drop.
Consequently, since the potentials at the terminals VR1 and VR2 become higher than the potentials at the bases of the NPN transistors Q4 and Q5, the potentials of the bit lines B1 and B2 exhibit values lower by the emitter-base voltages Vf of the NPN transistors Q6 and Q7 than those at the terminals VR1 and VR2, respectively. Consequently, the NPN transistors Q6 and Q7 are put into a conducting state.
Accordingly, current flows from the resistors RS1 and RS2 to the bit lines B1 and B2 and the constant current sources IR1 and IR2 through the NPN transistors Q8 and Q9, the data lines D1 and D2 and the NPN transistors Q6 and Q7, respectively. Then, if, in this condition, the potential of the word line VX2 of the memory cell 1 becomes high, then the MOS transistors MT1 and MT2 are put into a conducting state, and current Icell flows to the low potential side nodes of the memory cell 1.
In this instance, since the voltages across the resistors RS1 and RS2 are RS1.times.(IR1+Icell) and RS2.times.IR2, respectively, and here RS1=RS2 and IR1=IR2, a potential difference of RS1.times.Icell appears between output terminals Z1 and Z2. An output can be obtained by amplifying the potential difference by an amplifier in the next stage.
On the other hand, in a writing operation, similar steps of operation to those in the reading operation described above are followed until current Icell flows through the constant current sources IR1 and IR2 as the bit selection terminal VYIN1 is selected and the word line VX2 is selected. Then, in this condition, the potential at the terminal VR1 or VR2 is dropped. Here, if it is assumed that the potential at the terminal VR1 is dropped, then since the potential of the bit line B1 whose potential has dropped becomes a potential lower by the emitter-based voltage Vf than the potential at the terminal VR1, also the voltage of the node of the memory cell 1 which is connected to the bit line B1 drops. Consequently, the transistors MN2 and MP1 in the cell 1 are put into an off state while the transistors MP2 and MN1 are put into an on state, and data is written into the memory cell 1.
Thereafter, the writing operation can be completed by returning the potential at the terminal VR1 to the original high potential. Further, in this instance, since the bit line pair B1 and B2 in a non-selected condition is determined by the transistors Q4 and Q5 and exhibit high potentials, even if the voltage of the terminal VR1 drops, the voltages of the bit lines are not influenced by this, and consequently, no writing operation occurs.
It is to be noted that, in the memory circuit described above, since, as a characteristic of a memory circuit, normally a bit line pair is selected, current of the constant current sources IR1 and IR2 always flow to the data lines D1 and D2 and the potentials of the data lines D1 and D2 are fixed to voltages lower by the emitter-base voltage Vf of the NPN transistors Q8 and Q9 than the constant voltage source VBB.
As described above, in the conventional sense amplifier circuit of the current detection type, since a variation in current is read, even if the potentials at the data lines and the bit lines do not vary, data can be read.
However, the memory circuit shown in FIG. 5 has a subject to be solved in that it exhibits very high power dissipation if cells of a large scale are implemented.
The reason is that, in the conventional memory circuit shown in FIG. 5, since the constant current sources IB1 and IB2 are connected to the bit lines B1 and B2, respectively, current always flows to the constant current sources IB1 and IB2 through the transistors Q4 and Q5 also in those bit lines which are not selected. Consequently, if the number of bit lines is increased in order to increase the memory capacity, then also the current dissipation increases in proportion.
Further, the memory circuit shown in FIG. 5 has another subject to be solved in that it is difficult to achieve higher integration.
The reason is that a plurality of NPN transistors Q1 to Q7 are required for each bit line pair.
The reason why such NPN transistors Q1 to Q7 are required is that, since insulating isolation of MOS transistors can be established by an oxide film formed between the elements, augmentation of arrangement density of elements is easy and reduction in width of memory cells is easy whereas, in Bip elements, in order to isolate collector diffusion layers formed deep, where the voltages to the collectors are different, insulating regions must be formed between collector regions of the transistors and this requires a very large area. For example, where MOS transistors whose gate length is approximately 0.25 .mu.m are used, it is possible to set the width of each memory cell to 3 .mu.m or less, but the arrangement pitch of Bip transistors where they are formed based on the same rule as the MOS transistors is required to be 5 .mu.m or more.
Since the conventional memory circuit shown in FIG. 5 uses the NPN transistors Q1, Q2 and Q3 as switches, the NPN transistors Q1, Q2 and Q3 can be formed from MOS transistors. However, for the transistors Q4 to Q7, since the voltage Vf which appears between the base and the emitter is utilized, at least four NPN transistors are required for each one bit line pair. Consequently, it is difficult to arrange the NPN transistors with a width equal to the width of memory cells.
Furthermore, the conventional memory circuit shown in FIG. 5 has a further subject to be solved in that the speed is low because the potentials of the bit line pair vary upon switching of the bit line pair between a selected condition and a non-selected condition.
The reason is such as follows. In the conventional memory circuit, when a bit line pair is not to be selected, the potentials at the bit line pair are set so that the NPN transistors Q6 and Q7 exhibit a non-conducting state, but when the bit line pair is to be selected, the potential at the terminal VYIN1 is raised to a high potential so as to flow current to the constant current sources IR1 and IR2 to lower the potentials of the bit lines B1 and B2 to put the NPN transistors Q6 and Q7 into a conducting state. While the potentials of the bit lines B1 and B2 must be varied upon reading in this manner, the potential variation of the bit lines B1 and B2 does not occur momentarily due to an influence of additional capacitance parasitic to the bit lines B1 and B2 then. Particularly as the number of memory cells connected to one bit line pair is increased by higher integration, the delay becomes significant. Consequently, the switching time is delayed.